In the fabrication of dynamic random access memory (DRAM) arrays, gate material is typically patterned onto an insulating layer above a channel region. The gate material is typically surrounded by an insulating dielectric material deposited on top of the gate, with thin sidewalls extending down both sides of the gate. The dielectric material serves to insulate the gate from self-aligned source and drain contacts formed on either side of the gate.
In a DRAM array, the thickness of the insulating sidewalls is typically determined by the design rule and pitch of the array. For example, for a 0.3 micron design rule and a 0.6 micron pitch design, the sidewall thickness may be 500-700 Angstroms. For smaller design rules, the sidewall thickness may decrease to less than 300 Angstroms.
The DRAM array is typically surrounded on a chip by peripheral circuitry that includes metal oxide semiconductor field effect transistors (MOSFETs). To maximize efficiency in chip manufacturing, the gate deposition and insulating steps used in forming the DRAM array are typically used to simultaneously form the peripheral MOSFET gates. As a result, the sidewalls insulating the peripheral MOSFET gates will have the same thickness as the sidewalls in the DRAM array.
This peripheral sidewall thickness may not be the optimal thickness for MOSFET gate insulating sidewalls. For example, a source/drain implant is typically performed for peripheral MOSFETs after formation of the gate and insulating sidewalls, to separate the heavily doped portions of the source and drain regions from the channel region. This separation is necessary to prevent lateral diffusion of the source/drain dopant into the channel, and to reduce stress on the MOSFET device due to high electric fields at the source-channel junction and drain-channel junction.
Thus, if the design rule of the DRAM array does not allow for sufficiently thick sidewalls in the peripheral area, the physical channel lengths of the peripheral MOSFETs may have to be increased to maintain a given effective channel length due to lateral diffusion into the channel. Performance of the peripheral MOSFETs may also be affected due to increased stress at the source-channel and drain-channel junctions.